1. Field of the Invention
This invention relates to computing hardware, and more particularly to the architecture of registers in a processor capable of executing from two instruction sets.
2. Description of the Related Art
Processors, or central processing units (CPU's) that are capable of executing instructions from two separate instruction sets are highly desired at the present time. For example, a desirable processor would execute user applications for the x86 instruction set and the PowerPC.TM. instruction set. It would be able to execute the tremendous software base of x86 programs that run under the DOS.TM. and WINDOWS.TM. operating systems from Microsoft of Redmond, Wash., and it could run future applications for PowerPC.TM. processors developed by IBM, Apple, and Motorola. Such a processor is described in the related to the copending application for a "Dual-Instruction-Set Architecture CPU with Hidden Software Emulation Mode", filed Jan. 11, 1994, U.S. Ser. No. 08/179,926, now U.S. Pat. No. 5,781,750. That dual-instruction-set CPU has a pipeline which is capable of executing instructions from either a complex instruction set computer (CISC) instruction set, such as the x86 instruction set, or from a reduced instruction set computer (RISC) instruction set, such as the PowerPC.TM. instruction set.
Two instruction decode units are provided so that instructions from either instruction to set may be decoded. Two instruction decoders are required when the instruction sets are separate because the instruction sets each have an independent encoding of operations to opcodes. For example, both instruction sets have an ADD operation or instruction. However, the binary opcode number which encodes the ADD operation is different for the two instruction sets. In fact, the size and location of the opcode field in the instruction word is also different for the two instruction sets. In the x86 CISC instruction set, the opcode 03 hex is the ADD r,v operation or instruction for a long operand. This same opcode, 03 hex, corresponds to a completely different instruction in the PowerPC.TM. RISC instruction set. In CISC the 03 hex opcode is an addition operation, while in RISC the 03 hex opcode is TWI--trap word immediate, a control transfer instruction. Thus two separate decode blocks are necessary for the two separate instruction sets.
Programs may run in either or both instruction sets. Data and other information may be shared between RISC programs and CISC programs. One way to share data and other information is to store the data in a register within the CPU before switching to the alternate instruction set, and making all registers readable by either instruction set. Unfortunately, this requires that the instruction sets be extended to provide instructions to read the additional registers. The shared data could also be saved to a stack in memory, but this decreases performance due to the time required to transfer the data to memory and to adjust the stack pointers.
Two sets of registers could be provided; one set for the use of CISC programs and a second set for the use of RISC programs. This is an expensive approach since the registers reside on the CPU die, which has a limited space available for registers. The additional registers would require increasing the size of the CPU die, or deleting another function such as floating point processing.
What is desired is a way to share some of the registers between a CISC and a RISC architecture on a dual-instruction-set CPU. It is further desired lo have shared registers for data and system information. The shared registers should not be extra registers in addition to the registers already defined by the CISC or RISC architectures, but should be registers already existing in the architectures. The shared registers must not cause conflicts between use in the two instruction sets or other undesirable effects.